Abstract: Aiming at clock network’s function in SoC chip and its own characteristic, this paper studies and implements three kinds of clock low power consumption techniques including using dynamic clock management technique to cut down and distribute module’s clock dynamicly in system level, inserting clock gating cells based on power consumption optimization tool named Power Compiler during logic synthesis, and doing a low power consumption Clock Tree Synthesis(CTS) targeting on clock tree’s dimension during clock tree synthesis. These three techniques are implemented during the design of audio and video decoding chip, and the results show that their power consumption optimization effects are obvious.

Key words: clock, dynamic clock management, gated clock, low power consumption Clock Tree Synthesis(CTS)

摘要： 针对时钟网络在SoC芯片中的作用和时钟网络自身的特点，研究并实现3种时钟低功耗技术，包括在系统级采用动态时钟管理技术动态地关断和配置芯片内各模块的时钟，在逻辑综合时基于功耗优化工具Power Compiler插入门控时钟单元，在时钟树综合时以时钟树规模为目标进行低功耗时钟树综合。在音视频解码芯片的设计中采用以上3种技术，结果表明其功耗优化效果明显。

关键词: 时钟, 动态时钟管理, 门控时钟, 低功耗时钟树综合

CLC Number: 

• N945.15