Abstract: Flagged prefix adder has fast operation speed, but it has the disadvantage of large area. In order to meet the requirement of floating-point multiply and add cellar area for practical application, this paper gets 51 bit flagged prefix adder based on Kogge-stone tree structure by optimizing its structure. It uses module cascading to reduce the number of operation unit, attains the goal of reducing floating-point multiply, adding cellar area and decreasing power consumption. Under TMSC 0.18 μm technology, area, power and key path delay of this 51 bit adder are decreased respectively by 10%, 10.5% and 6.4%.

Key words: flagged prefix adder, floating-point operation, structure optimization

摘要： 标志前缀加法器运算速度快但存在面积大的缺点。为满足实际应用中对浮点乘加单元面积的要求，对其进行结构优化得到基于Kogge-stone树结构的51位标志前缀加法器，采用模块级联减少运算单元个数，达到减小浮点乘加单元面积、降低功耗的目的。在TMSC 0.18 μm工艺下，该51位加法器的面积、总功耗、关键路径时延分别减少了10%, 10.5%, 6.4%。

关键词: 标志前缀加法器, 浮点运算, 结构优化

CLC Number: 

• TP393