Abstract: This paper designs a multi-core sharing SDRAM controller based on network processing, presents a hierarchical priority arbitration algorithm to improve the efficiency of accessing shared memory for the multi-core. For the IP packet processing features, a block data transfer mechanism based on the instruction control is presented, which can shorten the latency of processing IP packet. Priority algorithm and block data transfer mechanism are verified on FPGA platform. Results indicate that processing the IP packet of 64 Byte, SDRAM controller can improve the reading and writing efficiency by 55% at least.

Key words: hierarchical priority arbitration, block data transfer, SDRAM controller

摘要： 设计一种基于网络处理的多核共享SDRAM控制器，提出分层优先级仲裁算法以提高多核访问共享内存的效率，针对IP包处理特点，给出一种基于指令控制的块数据传输机制来缩短IP包的读写延迟。在FPGA平台上进行验证，结果表明，当处理长度为64 Byte的IP包时，SDRAM控制器的读写效率能提高55%以上。

关键词: 分层优先级仲裁, 块数据传输, SDRAM控制器

CLC Number: 

• TP393