Abstract: This paper focuses on the design of Viterbi decoder for the Ultra-WideBand(UWB) wireless system. It improves the hybrid survivor path management unit in the decoder, promoting its maximum operating speed by 25% and reduces its decoding latency by 40 clocks. The implementation result on the Xilinx Virtex-5 XC5VLX330 FPGA shows the Viterbi decoder this paper presents can work correctly at 240 MHz. The data transmitted at all the eight kinds of speed can be decoded by using two slices of such Viterbi decoder in parallel.

Key words: Ultra-WideBand(UWB), Viterbi algorithm, hybrid survivor path management

摘要： 提出一种超宽带系统中的维特比译码器，对混合幸存路径管理单元进行改进，使其最高工作频率提升25%，译码延时减少40个时钟周期。在Xilinx Virtex-5 XC5VLX330 FPGA上的实现结果表明，该维特比译码器能在240 MHz的时钟频率下正确工作。并行使用 2个该译码器，可对系统中所有8种速率的数据译码。

关键词: 超宽带, 维特比算法, 混合幸存路径管理

CLC Number: 

• TN764