Abstract:
In study of Network-on-Chip(NoC) traffic generation and reception model, IP core architecture is presented which supports multiple various traffic model. It offers microprocessor interface, through configuration register parameter to produce a specific flow of data packets, and by reading the register to get throughput, packet delay and error statistics network performance indicator data. Based on CMOS technology SMIC 0.13 μm, the chip is designed and implemented. The frequency is up to 300 MHz, and it can meet different topologies network on-chip traffic requirements.
Key words:
Network-on-Chip(NoC),
traffic model,
IP core
摘要： 研究片上网络流量产生与接收模型，提出支持多种流量模型的IP核体系结构。提供微处理器接口，通过配置寄存器参数产生特定流量的数据包，并使用读寄存器得到吞吐量、延时和误码等网络性能指标数据。芯片的设计与实现基于SMIC0.13 μm标准CMOS工艺，工作频率可达到300 MHz，满足不同拓扑结构的片上网络流量产生要求。
关键词:
片上网络,
流量模型,
IP核
CLC Number:
QI E-Jun, JIANG Lin. Network-on-Chip IP Core Traffic Model Research and VLSI Design[J]. Computer Engineering, 2010, 36(24): 239-240.
支亚军, 蒋林. 片上网络IP核流量模型研究与VLSI设计[J]. 计算机工程, 2010, 36(24): 239-240.