Abstract: By the analysis of the architectures of parallel computer, an embedded data parallel computer architecture model is proposed for multimedia processing applications. The limitations of high communication complexity and weak adaptability of the conventional PIM architectures is bridged by this model combined the PIM technology with the reconfigurable bus. The main components and the instruction set are described in detail. A typical algorithm example is given to show the composition of assembly language program and the process of parallel computation.

Key words: PIM technology, data parallel architecture, reconfigurable bus, Processing Element(PE) array, instruction set architecture

摘要： 通过对国内外并行计算机体系结构的分析与研究，提出一种面向多媒体应用的嵌入式数据并行计算机体系结构模型，将可重构总线与PIM技术相结合，弥补传统PIM体系结构下处理元之间通信复杂度高、结构可适应性弱等不足。

关键词: PIM技术, 数据并行体系结构, 可重构总线, 处理元阵列, 指令集体系结构

CLC Number: 

• N945