Abstract: In the research of digital circuit evolution, sequential circuit evolution is very hard task because it is inconvenient to be described and simulated for the existence of feedback loop. In this paper, a single-layered fully-connected circuit network model is constructed using D flip-latch and logic gate as the basic element, and the one-to-one mapping existed in the mathematical encoding, circuit topology, and HDL file is established. The method to obtain Hardware Description Language(HDL) file according to circuit encoding is designed, the circuit evaluation process was automated by using of batch processing technology. Experiment of fourfold frequency divider proved the feasibility and validity of the method.

Key words: extrinsic evolution, synchronous sequential circuit, circuit simulation, Hardware Description Language(HDL), Evolutionary Strategies(ES)

摘要： 时序电路存在反馈环，不便于电路描述和软件仿真，很难进行演化。为此，以D触发器和逻辑门为基本单元，构建描述时序电路的全向连接电路网络模型。建立电路编码、电路拓扑与硬件描述语言(HDL)代码文件之间的映射关系，设计由电路编码获取相应HDL代码的方法，利用批处理技术实现电路评估过程的自动运行。四倍分频器电路演化实验结果验证了该方法的可行性与有效性。

关键词: 外部演化, 同步时序电路, 电路仿真, 硬件描述语言, 进化策略

CLC Number: 

• TP302.1