Abstract: A cipher System on a Chip(SoC) platform is designed against the lack of applicability of current cipher SoC platform. Special-designed cipher coprocessor is integrated to realize several cryptographic algorithms and power reduction of the platform is reduced by adaptive clock gate control unit in system level. Several high and low speed communication interfaces are also supplied to complete external data exchange. Experi- mental results show that the platform can support different cipher operations effectively with lower power dissipation and higher data throughput.

Key words: System on a Chip(SoC), cipher coprocessor unit, adaptive clock gate control unit, communication interface, Field Programmable Gate Array(FPGA)

摘要： 针对密码片上系统(SoC)平台适用性不高的问题，设计实现一种高性能低功耗的密码SoC平台。集成自主设计的密码协处理器单元，支持多种密码算法，设计自适应门控单元，实时调整时钟状态，提供多种高低速通信接口，以完成对外数据交换。实验结果表明，该平台能完成多种密码操作，具有较低的功耗和较高的数据吞吐率。

关键词: 片上系统, 密码协处理器单元, 自适应时钟门控单元, 通信接口, 现场可编程门阵列

CLC Number: 

• N945