Abstract: The average penalty of Level 1 Instruction Cache(L1 I-Cache) is simply quantified for the next level storage access time, this simple quantitative introduces large errors during analysis of performance bottlenecks. Aiming at the problem, this paper uses interval model to analyze what are the front-end factors that impact on the average penalty, and validate the analytical results through simulation experiments. Result shows that in addition to the next level of cache or main memory access time, fetch bandwidth, the size of the fetch queue, the L1 I-cache miss rate, the branch misprediction rate and the program characteristic can impact on the average of L1 I-Cache miss penalty.

Key words: superscalar processor, Level 1 Instruction Cache(L1 I-Cache), miss penalty, interval model

摘要： 一级指令Cache的平均缺失损失被量化为下一级存储系统的访问时间，在进行处理器性能瓶颈分析中简单的量化会引起较大的误差。针对该问题，应用区间模型分析影响一级指令Cache平均缺失损失的前端因素，并用模拟实验进行分析研究，结果表明，除下一级存储系统的访问时间外，取指带宽、取指队列的大小、一级指令Cache缺失率及程序特性，会对一级指令Cache平均缺失损失产生影响。

关键词: 超标量处理器, 一级指令Cache, 缺失损失, 区间模型

CLC Number: 

• TP391