Abstract: For the purpose of verification of the memory consistency model after tapeout stage, this paper proposes a low time complexity algorithm by exploring the key time order information which is implicitly derived based on the values of performance counters being scanned periodically. The MOTEC tool which implements this algorithm is general enough to support many multicore processor systems with trivial modifications. The complexity analysis shows that the time complexity of MOTEC is only , thus MOTEC can verify the multicore program of millions of lines.

Key words: multicore processor, memory consistency model, formal verification, dynamic validation, memory system, validation tool

摘要： 由于缺乏可利用的额外观察条件，在芯片流片后阶段进行存储一致性模型验证较困难。为此，利用多核处理器系统中通用的性能计数器，通过定期扫描性能计数器以获得关键活动访存指令集合的信息，实现MOTEC工具。该工具由MOTEC随机指令发生模块、多核处理器性能计数器记录模块和MOTEC分析模块3个部分组成。对其核心算法的分析结果表明，MOTEC的时间复杂度仅为 ，在目前流片后阶段进行验证的工具中时间复杂度最低。

关键词: 多核处理器, 存储一致性模型, 形式验证, 动态验证, 存储系统, 验证工具

CLC Number: 

• TP311.5