Abstract: This paper analyzes the point multiplication in EC and educes the modular multiplication formula in GF(2m) for systolic implementation with partial-parallelism in MSB mode. Following the formula, it designs an efficient architecture of systolic array, studies the performance of the array element and compares with the performance in LSB mode. The simulation result proves that the partial-parallel architecture in MSB mode which supports flexible irreducible polynomials of GF(2m) can process modular multiplication efficiently with proper hardware cost, while the partial-parallel architecture which supports fixed irreducible polynomials can save the hardware cost and archive high performance at the same time. Both can improve the performance of ECC algorithms in GF(2m) efficiently.

Key words: finite field, modular multiplication, systolic array, partial-parallel, MSB

摘要： 在分析EC上点乘操作的基础上，构造了MSB方式下局部并行线性systolic结构的模乘递推形式，设计了具体的单元结构，给出了性能分析和模拟比较结果。实验证明MSB方式下局部并行、域多项式可变的阵列结构能适应多种EC上模乘，实现灵活、高速的模乘处理，而局部并行、固定域多项式结构能在较优的硬件代价下高效实现特定EC上模乘，有效提高GF(2m)上ECC算法的性能。

关键词: 有限域, 模乘, systolic阵列, 局部并行, 高位优先

CLC Number: 

• TP303