Abstract: This paper presents a floating-point Sparse Matrix Vector Multiply(SMVM) on reconfigurable computing platform, because traditional implementation SpMXV on General Purpose Processor(GPP)is very inefficient. The design of SpMXV co-processor is based on IEEE-754 32 bit floating point data formats, diagonal storage scheme and the binary tree data flow. The implementation on reconfigurable computing platform is pipeline and highly efficient parallel. Simulation results illustrate that SpMXV on a reconfigurable computing platform can speedup over the software version of the same algorithm about 2.69 times.

Key words: reconfigurable computing, co-processor, sparse linear equations, Sparse Matrix Vector Multiply(SMVM), reduction array

摘要： 针对传统的通用处理器(GPP)平台上执行稀疏矩阵向量乘计算效率低的问题，提出一种基于可重构计算平台的SpMXV协处理器设计。方案采用二叉树结构高度流水的数据流、IEEE-754的32 bit浮点数数据格式和对角存储格式。数据通路以流水线方式进行组织，能够优化计算性能。仿真结果表明，与GPP平台上的软件实现相比，通过硬件实现的设计能达到最高2.69倍的性能加速。

关键词: 可重构计算, 协处理器, 稀疏线性方程组, 稀疏矩阵向量乘, 归约阵列

CLC Number: 

• TP391