Abstract: For System on Chip(SoC) architecture design, the simulation speed of Register Transfer Level(RTL) modeling is slow, and system modeling using C language lacks of enough accuracy. To solve these problems, this paper presents a Cache Transaction Level Modeling(TLM) method with cycle-accurate and bits-accurate, using electronic system level design methodology. In the model, different abstraction layers are adopted in the external interfaces and internal logic. The SoC is constructed based on the Electronic System Level(ESL) design, and realizes the S/H co-design. Experimental results show that the simulation platform with the Cache model is significantly reduced in the number of cycles when running the corresponding program, and achieves the established accuracy requirements.

Key words: Cache, Electronic System Level(ESL) design, Transaction Level Modeling(TLM), System on Chip(SoC) architecture design, cycle-accurate, software/hardware co-design

摘要： 对于片上系统(SoC)架构设计，寄存器传送级建模仿真速度慢，而采用C语言建模达不到所需的精度要求。针对上述问题，基于电子系统级(ESL)设计方法，提出一种通用的周期精确/位精确的高速缓存(Cache)事务级模型。该模型面向外部接口和内部逻辑分别采用不同的抽象层次进行建模，并构建基于ESL设计的SoC，实现软硬件协同设计。实验结果表明，集成Cache模块的仿真平台运行相应程序所需周期数大幅减少，可达到既定的精度要求。

关键词: 高速缓存, 电子系统级设计, 事务级建模, 片上系统架构设计, 周期精确, 软/硬件协同设计

CLC Number: 

• TP316