星载FlexRay数据总线自主可控IP核的设计与验证

doi:10.19678/j.issn.1000-3428.0069963

摘要/Abstract

摘要：

传统的星载数据总线控制器局部网(CAN)和1553B总线难以满足日益复杂的空间探测任务需求。地面成熟的FlexRay总线以其高速率、确定性、高可靠、拓扑灵活、低成本等优势, 成为新型星载数据总线的研究热点。但FlexRay总线自主可控芯片欠缺且相关器件主要面向汽车领域, 限制了其在航天领域的部署应用。针对FlexRay总线协议复杂、星载任务可靠性要求高、受体积质量限制较大等技术难点, 提出一种自主可控的高可靠FlexRay协议IP核的设计。通过自启动设计, 解决FlexRay节点必须配备主机导致的成本、体积、质量增加问题; 提出一种特殊消息帧负载段格式和处理方式, 实现无主机节点的在轨维护; 设计一种消息过滤方法, 减少FlexRay节点不必要的消息处理开销; 分析三模冗余方法, 可有效减小单粒子翻转的影响; 设计多种错误处理方式, 有效防止异常节点干扰FlexRay网络。最后, 通过Modelsim仿真测试、硬件测试平台测试以及示波器测试, 对设计的FlexRay IP核进行功能、性能、可靠性测试, 结果表明, 该IP核与国外成熟的FlexRay芯片兼容, 支持多节点通信, 误码率小于10^-12。

关键词: FlexRay总线, 现场可编程门阵列, IP核, 星载, 自主可控, 数据总线

Abstract:

Traditional spacecraft data buses such as Controller Area Network (CAN) and 1553B struggle to meet the increasingly complex demands of modern spaceborne missions. FlexRay, a bus technology that has matured in ground-based applications, has emerged as a research hotspot for next-generation spacecraft data buses owing to its advantages in high speed, determinism, reliability, flexible topology, and low cost. However, the absence of autonomous and controllable FlexRay-compatible chips-and the fact that existing components are primarily designed for the automotive industry-has limited its deployment and application in China's aerospace sector. To address technical challenges such as the complexity of the FlexRay bus protocol, the high reliability requirements of spaceborne missions, and strict constraints on volume and mass, this paper proposes the design of an autonomous, highly reliable FlexRay protocol IP core. The self-starting architecture eliminates the need for an external host at each FlexRay node, thereby reducing system volume and mass. In addition, a specialized message frame format and processing method are designed to enable onboard maintenance of hostless nodes. A message filtering method is designed to reduce unnecessary message processing overhead in FlexRay nodes. The triple modular redundancy method, which effectively mitigates the impact of a single event upset, is also analyzed. Various error handling methods are developed to prevent abnormal nodes from interfering with the FlexRay network. Finally, the functionality, performance, and reliability of the designed FlexRay IP core are verified through Modelsim simulation, hardware testing, and oscilloscope analysis. Experimental results show that the IP core is compatible with a mature foreign FlexRay chip, supports multinode communication, and achieves a bit error rate of less than 10^-12.

Key words: FlexRay bus, Field Programmable Gate Array (FPGA), IP core, satellite-borne, autonomous and controllable, data bus

李云佳赟, 安军社, 周莉. 星载FlexRay数据总线自主可控IP核的设计与验证[J]. 计算机工程, 2025, 51(12): 311-323.

LI Yunjiayun, AN Junshe, ZHOU Li. Design and Verification of Autonomous and Controllable IP Core for Satellite-Borne FlexRay Data Bus[J]. Computer Engineering, 2025, 51(12): 311-323.

https://www.ecice06.com/CN/Y2025/V51/I12/311

图/表 28

图1 FlexRay节点结构

Fig.1 FlexRay node structure

图2 FlexRay时间层次

Fig.2 FlexRay time hierarchy

图3 静态段通信机制

Fig.3 Static segment communication mechanism

图4 动态段通信机制

Fig.4 Dynamic segment communication mechanism

图5 数据帧格式

Fig.5 Data frame format

图6 搭载设计IP核的FlexRay节点结构

Fig.6 FlexRay node structure equipped with the designed IP core

图7 FlexRay内核架构

Fig.7 FlexRay kernel architecture

图8 POC状态转换

Fig.8 POC state transition

图9 启动状态转换

Fig.9 Startup state transition

图10 接收FIFO范围帧ID滤波控制寄存器

Fig.10 Receive FIFO range frame ID filter control register

图11 FIFO范围帧ID滤波器流程

Fig.11 Procedure of FIFO range frame ID filter

图12 触发器三模冗余

Fig.12 TMR of flip-flop

图13 配备主机IP核功耗和无须配备主机IP核功耗

Fig.13 Power consumption of IP core requiring host and power consumption of IP core not requiring host

图14 正常启动和同时启动时的协议运行转换

Fig.14 Protocol operation conversion during normal startup and simultaneous startup

图15 读无主机节点

Fig.15 Read hostless nodes

图16 写无主机节点

Fig.16 Write hostless nodes

图17 节点1和节点2在通道B的发送与接收

Fig.17 Sending and receiving of node 1 and node 2 in channel B

图18 节点2在通道A的8时隙接收数据

Fig.18 Node 2 receives data in time slot 8 of channel A

图19 FPGA板间测试ChipScope波形

Fig.19 ChipScope waveform tested between FPGA boards

图20 兼容性测试

Fig.20 Compatibility test

图21 误码率测试

Fig.21 Bit error rate test

图22 通信信道上的数据帧传输起始

Fig.22 Start of a data frame transmission on communication channel

图23 静态时隙持续时间

Fig.23 Static time slot duration

图24 周期持续时间

Fig.24 Cycle duration

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