Abstract: This paper proposes a compact and low cost architecture for AES encrypt and decrypt. As the mathematical manipulation lies on finite filed computation, the orders of the round operation are modified so that the design can reuse some modules to save the area. Meanwhile the element inversion in the SubByte module is performed by composite field technique and the area and power consumption is reduced significantly. Based on the HHNEC 0.25μm CMOS technology, area of the design is about 30k equivalent gates and its system frequency will be up to 100MHz. The operation speed of the 128bits data encryption and decryption is as high as 800Mbps.

Key words: AES, Low cost, SubByte, Composite field

摘要： 提出了一种先进密码算法(AES)的低成本VLSI实现方案。从分析AES算法入手，优化运算次序，实现相应模块的复用，从而达到缩小芯片面积的目标，同时将关键的字节替换(SubByte)模块转化到对应的复合域中进行运算，进一步减小芯片复杂度。基于HHNEC 0.25μm标准CMOS工艺，芯片工作频率可以达到100MHz，密钥为128bits时，芯片的加解密速度可达800Mps，而芯片规模不超过 30K门。

关键词: AES, 低成本, 字节替换, 复合域