Abstract: Aiming at the structure of compute-intensive SoC that “one RISC main processor core + some dedicated co-processor cores”, this paper designs a memory access structure which supports a command-driven chunk data transfer. The structure is optimized with block-transfer and pipeline-transfer support. Experimental results show that the structure after optimization has high efficiency, low cost and well flexibility.

Key words: Scratchpad Memory(SPM), multicore-SoC, memory access

摘要： 针对“一个RISC主处理器核+几个专用协处理器核”结构的计算密集型SoC，设计一种以执行命令方式完成大块数据传输的高效访存结构。通过增加组传输和流水传输模式，对该结构进行优化。实验结果表明，该访存结构设计及优化方案的数据传输效率高、实现开销小，并且对同类SoC系统，该设计具有良好的适用性。

关键词: 便签式存储器, 多核SoC, 访存

CLC Number: 

• TP303