Design of Memory Access Structure for Coarse-Grained Reconfigurable Array with Decoupled Access Execute

doi:10.19678/j.issn.1000-3428.0056726

Abstract

Abstract: Coarse-Grained Reconfigurable Array(CGRA) architecture has both flexibility and efficiency,but its characteristics of high computing throughput also brings pressure to memory.In the case of the relative fixed bandwidth of off-chip Dynamic Random Access Memory(DRAM),this paper designs a memory access structure based on Decoupled Access Execute(DAE).This structure integrates the control logic into the lightweight buffer storage,and uses configurable storage space to isolate the iteration of memory access and computation to hide memory latency.In addition,this structure can be chained or aligned to adapt to different computing memory-access frequency ratio and optimize indirect access.Experimental results show that this decoupled memory access structure can improve the performance 1.84 times in the target architecture,and alignment operation can provide 22% performance improvement in average for indirect access.

Key words: Coarse-Grained Reconfigurable Array(CGRA), memory latency, Decoupled Access Execute(DAE), indirect access, memory access structure

摘要： 粗粒度可重构阵列架构兼具灵活性和高效性，但高计算吞吐量的特性也会给访存带来压力。在片下动态存储器带宽相对固定的情况下，设计一种存算解耦合的访存结构。将控制逻辑集成在轻量级的存储空间中，通过可配置的存储空间隔离访存和计算的循环迭代，从而掩盖内存延时，同时利用该结构进行串联和对齐操作，以适配不同的计算访存频率比并优化间接访问过程。实验结果表明，该访存结构在目标架构中能够获得1.84倍的性能优化，其中乱序操作可使间接访问得到平均22%的性能提升。

关键词: 粗粒度可重构阵列, 内存延时, 存算解耦合, 间接访问, 访存结构

CLC Number:

TP303

HONG Tu, JING Naifeng. Design of Memory Access Structure for Coarse-Grained Reconfigurable Array with Decoupled Access Execute[J]. Computer Engineering, 2021, 47(2): 239-245.

洪途, 景乃锋. 存算解耦合的粗粒度可重构阵列访存结构设计[J]. 计算机工程, 2021, 47(2): 239-245.

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References 21

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