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XIE Chuang,YANG Zhijia,WANG Jian.
Design of Industrial Wireless System-on-Chip Based on TSCH Mode
[J]. Computer Engineering, 2018, 44(6): 288-293,299.
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YIN Yingying,YU Zhiyi.
Research on In-memory Computing Based on 2.5D Integrated System
[J]. Computer Engineering, 2017, 43(2): 105-110,119.
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SHI Longzhao,GUO Jimin.
Design of Low Power Consumption FFT/IFFT Processor in MIMO-OFDM System
[J]. Computer Engineering, 2016, 42(7): 16-21.
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HUANG Kai,LIN Wei,JIANG Jinsong,HU Teng,XIU Siwen,YAN Xiaolang.
Design of Low-power and Configurable IP Core for USB 3.0 Device Controller
[J]. Computer Engineering, 2015, 41(12): 1-8.
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XIU Yujie,HUANG Kai,LIN Wei,YU Min,MO Pengfei,YAN Xiaolang.
SoC Concurrent Clock Scheduling Management Oriented to Shared Resource Conflict
[J]. Computer Engineering, 2015, 41(9): 108-114.
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SUN Chen,ZHAO Yiqiang,LIU Qiang,LI Xu.
Optimal Design of Cascaded Integrator Comb Interpolation Filter in Broadband Communication Chip
[J]. Computer Engineering, 2015, 41(8): 252-255,261.
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XU Tailong,XUE Feng,GAO Xianhe,CAI Zhikuang,HAN Shaoyu,HU Xueyou,CHEN Junning.
Design of All Digital SARDLL for DVFS System-on-Chip
[J]. Computer Engineering, 2015, 41(4): 273-276,283.
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HUANG Rui, YANG Qing-qing, CHENG Jie-qiong, ZHOU Xiao-fangPPPP.
Design of Application Specific Control Processor for LDPC and Turbo Decoder
[J]. Computer Engineering, 2014, 40(7): 1-6.
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XU Tai-long, XUE Feng, CAI Zhi-kuang, ZHENG Chang-yong.
Design of Fast All Digital Successive Approximation Register Delay-locked Loop
[J]. Computer Engineering, 2014, 40(4): 262-268.
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ZHENG Zhao-xia, LI Yi-fan, YU Liang, TIAN Yuan, LIU Zheng-lin.
Hardware Trojan Detection Technology Based on Probabilistic Signature
[J]. Computer Engineering, 2014, 40(3): 18-22.
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XU Tai-long, LU Shi-bin, DAI Guang-zhen, MENG Jian, CHEN Jun-ning.
A Testability Design Scheme for Low Power Consumption System-on-Chip
[J]. Computer Engineering, 2014, 40(3): 306-309.
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ZHANG Dun, CHEN Hai-Bin.
Design of All-digital Clock Recovery Unit Based on USB Device
[J]. Computer Engineering, 2012, 38(14): 231-233.
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YANG Wen-Long, CHEN Li, WANG Ling-Li, WANG Ying.
Radioresistance Placement Algorithm for FPGA Based on SRAM Structure
[J]. Computer Engineering, 2012, 38(5): 236-239.
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CHEN Hai-Min, LI Zheng, XIE Tie-Du.
Optimal Design of Multiplier Based on Radix-4 Booth Encoding
[J]. Computer Engineering, 2012, 38(01): 233-235.
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CUI Feng, CHEN Li-Guang, LAI Jin-Mei, ZHOU Hao, BAO Li-Chun.
Design and Implementation of SEU Hard Core Detection Circuit
[J]. Computer Engineering, 2011, 37(20): 252-254.
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