Abstract:
The ABC95 processor array is a SIMD parallel computer with 16 processing clements. The main problem when implementing itusing FPGA is the too low using rate. In this paper, we introduce several optimization methods, using FPGA to implement the ALU.multiplier and instruction decoder. Because reducing the number of signals of each part, the problem is solved.
摘要： ＡＢＣ９５阵列机是１６个节点组成的ＳＩＭＤ并行计算机．在用ＦＰＧＡ设计实现此机器时的主要问题是ＦＰＧＡ利用率太低。介绍几种优化手段，将ＡＬＵ、乘法器和译码器都用ＦＰＧＡ实现。这样减少了系统各模块之间的连线数，达到了提高ＦＰＧＡ利用率的目的。
关键词:
FPGA,
阵列机,
设计优化
CLC Number:
Tong Dong, Li Dongmei, Zhou Yonglin, Fang Binxing. The Implementation and Optindzation of ABC95 Processor Array Using FPGA[J]. , 1999, 25(12): 43-45.
佟冬,黎冬梅,周永林,方滨兴. ABC95阵列机的FPGA实现及其优化[J]. , 1999, 25(12): 43-45.