Analysis and Generation of Bus-level Fault Model

›› 2000, Vol. 26 ›› Issue (02): 65-67.

• Papers • Previous Articles Next Articles

Analysis and Generation of Bus-level Fault Model

Sun Junzhao, Yang Xiaozong, Liu Jialin

(Dept. of Computer Science and Engineering, Harbin Institute of Technology, Harbin 150001; Sales Department, Heilongjiang Subsidiary Bank of China Construction Bank. Harbin 150076)

Published:2000-02-25

总线级故障模型的分析与生成

孙峻朝,杨孝宗,刘嘉林

哈尔滨工业大学计算机科学与工程系哈尔滨 150001,哈尔滨工业大学计算机科学与工程系哈尔滨 150001,中国建设银行黑龙江省分行营业部哈尔滨 150076

Abstract

Abstract: In this paper, the attributes of bus-level fault model(BLFM) are analyzed. The generation process of BLFM is discussed. A case study is presented to demonstrat the effectiveness of our methods.

摘要： 针对总线级故障模型，对其属性进行了分析，讨论了模型的生成过程，以一个应用实例说明了文中所提方法的有效性。

关键词: 容错机制, 故障注入, 总线级故障模型, 双向模拟

CLC Number:

TP302.8

Sun Junzhao, Yang Xiaozong, Liu Jialin. Analysis and Generation of Bus-level Fault Model[J]. , 2000, 26(02): 65-67.

孙峻朝,杨孝宗,刘嘉林. 总线级故障模型的分析与生成[J]. , 2000, 26(02): 65-67.

[1]	LIU Ruitao,CHEN Zuoning. Supercomputers memory faults analysis based on statistical data [J]. Computer Engineering, 2019, 45(5): 35-45.
[2]	ZHANG Peng,ZHU Li,DU Xiaozhi,HE Chaohui,CHEN Hao. Control Flow Error Detection Algorithm Based on Structural Tag [J]. Computer Engineering, 2016, 42(6): 37-42.
[3]	LEI Changjian,LIN Yaping,LI Jinguo,ZHAO Jianghua. Research on Byzantine Fault Tolerance Under Volunteer Cloud Environment [J]. Computer Engineering, 2016, 42(5): 1-7.
[4]	WANG Ze-Cheng, YOU Zhi-Jiang. Delay Test Method Based on Scan Chain Blocking Technique [J]. Computer Engineering, 2012, 38(04): 205-207.
[5]	BO Yang, MA Man-Fu, NIU Ceng-Han. Fault-tolerance of QoS Parameters in Grid Schedule [J]. Computer Engineering, 2011, 37(7): 44-46,49.
[6]	ZHANG Yun, YOU Zhi-Jiang, KUANG Ji-Shun, BANG Fu-Hui. Low-power and Low-cost Test Approach Based on TSP [J]. Computer Engineering, 2011, 37(4): 281-283.
[7]	LI Deng-jing; FAN Shou-wen. Design of Dual CPU Fault-tolerant Controller Based on FPGA [J]. Computer Engineering, 2010, 36(2): 238-240.
[8]	GU Xiao-dan; XIAO Wei; ZHANG Fan. Research on Disaster Tolerance Policy of Aerospace TT&C System [J]. Computer Engineering, 2009, 35(24): 150-152.
[9]	CHU Jie; YUAN Liang; ZHAO Qiang; DING Guo-liang; WU Cai-hua. Motor Control System with High Reliability Based on TMR-EHW [J]. Computer Engineering, 2009, 35(23): 10-11,1.
[10]	XU Qiang; XU Kai. Design and Application of Multi-MCU Fault-tolerance Based on C/OS-II [J]. Computer Engineering, 2008, 34(17): 281-283.
[11]	HAO Yong-jie; JIANG Jian-guo;. Improved Time-domain Decoding Algorithm of RS Code [J]. Computer Engineering, 2008, 34(14): 104-106.
[12]	YANG Yun; CHEN Liya. Design and Implementation of Bandwidth-plan Algorithm in Fault-tolerant Optical Network [J]. Computer Engineering, 2007, 33(10): 120-122.
[13]	LI Haishan; OU Zhonghong; YANG Shengchun; YUAN Youguang. COTS-based Fault-tolerant Server and Its Fault Recovery Techniques [J]. Computer Engineering, 2007, 33(08): 253-255.
[14]	LIU Dong; ZHANG Chunyuan; LI Rui. Dual Fault-tolerant System Based on Task-level Synchronization [J]. Computer Engineering, 2007, 33(08): 224-226.
[15]	YUAN Liang; DING Guoliang; LIU Wenbing; HUANG Feiyun; ZHAO Qiang. TMR Hardening and Its Application in Control System [J]. Computer Engineering, 2006, 32(21): 249-251.

Please choose a citation manager

Content to export

Analysis and Generation of Bus-level Fault Model

总线级故障模型的分析与生成

PDF

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics

Comments

模态框（Modal）标题

Please choose a citation manager

Content to export

Analysis and Generation of Bus-level Fault Model

总线级故障模型的分析与生成

PDF

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics

Comments