Application of VHDL Language in Testifying Predicate_Logic Whose Universe D is{0,1}

›› 2003, Vol. 29 ›› Issue (02): 91-92.

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Application of VHDL Language in Testifying Predicate_Logic Whose Universe D is{0,1}

LENG Ming，TANG Yi，WU Yue，YANG Hongbin

(School of Computer Engineering and Science, Shanghai University, Shanghai 200072)

Published:2003-01-25

VHDL语言在个体域D为{0,1}的谓词逻辑定理证明中的应用

冷明,唐毅,吴悦,杨洪斌

上海大学计算机学院,上海大学计算机学院,上海大学计算机学院,上海大学计算机学院上海 200072, 上海 200072, 上海 200072, 上海 200072

Abstract

Abstract: This paper proposes the application of VHDL language in testifying Predicate_Logic whose universe D is{0,1}, and exemplifies in Active-HDL。

摘要： 提出了以VHDL语言为手段，介绍了针对个体域D为{0,1}的谓词逻辑定理证明的实现方法，并在Active-HDL环境中举例说明。

关键词: VHDL语言, 谓词逻辑, 定理证明

CLC Number:

TP312

LENG Ming，TANG Yi，WU Yue，YANG Hongbin. Application of VHDL Language in Testifying Predicate_Logic Whose Universe D is{0,1}[J]. , 2003, 29(02): 91-92.

冷明,唐毅,吴悦,杨洪斌. VHDL语言在个体域D为{0,1}的谓词逻辑定理证明中的应用[J]. , 2003, 29(02): 91-92.

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Application of VHDL Language in Testifying Predicate_Logic Whose Universe D is{0,1}

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Application of VHDL Language in Testifying Predicate_Logic Whose Universe D is{0,1}

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