Abstract:
This paper gives a high-speed data buffer interface circuit based on field programmable gate array (FPGA). Under the control of this circuit unit, the data can be reliably transformed from outer instrument to hi-speed serial color display. It is used in an intelligent building control and administration system to display system state and alarm parameter.
摘要: 提出了一种以FPGA为控制核心的高速数据缓冲接口电路,在其控制下低速外设输入的数据能可靠地与高速串行彩色显示器进行数据传输。将其运用于智能小区的信息显示系统中,显示系统的各种状态参数和报警参数。
关键词:
FPGA,
显示器,
随机存储器
CLC Number:
TU Yunwu1,HUANG Jinbo2,SHEN Xu2. Interface Technology of Hi-speed Data Buffer Based on FPGA[J]. , 2003, 29(20): 146-.
屠运武,黄金波,沈旭. 基于FPGA控制的高速数据缓冲接口技术[J]. , 2003, 29(20): 146-.