Abstract: Small area is required for cipher chips used in portable devices such as smart card and PDA etc.The requirement for hardware resource is dramatically decreased by careful optimization of the AES algorithm.The optimized AES architecture is described by Verilog HDL and implemented with Altera APEX20K device.The validated FPGA prototype integrates both the encryption and decryption modes and all the three kinds of key length,which is suitable for the future VLSI implementation of the AES.

摘要： 在智能卡、PDA等便携式设备中,希望使用面积小的密码芯片。通过对AES算法进行结构优化,有效地减小了硬件实现时的开销。使用Verilog HDL语言设计并在Altera APEX20K器件中验证通过,设计集成了加密/解密模式及所有3种密钥长度,为进一步的VLSI实现提供了FPGA原形验证。

关键词: 高级加密标准, CMOS, 逻辑综合, FPGA

CLC Number: 

• TP309.7