Abstract: Due to the increasing system complexity of hardware design,functional verification becomes the bottleneck of the design flow.General processor is one of the most complex designs of integrated circuits,and it brings a huge challenge on its functional verification.This paper proposes a constraint random instruction generation method,for the simulation-based verification of an ARMv8 processor.This instruction generation method is based on the templates that are extracted from the instruction set,which guide the valid ARMv8 instructions’ generation,and can support a variety of functional scenarios’ verification by adjusting the constraints.Based on automatically comparison of the results produced by the validation environment,it achieves fully verification of the processor,and 58 design mistakes are found.The achievement has a good foundation,for the subsequent FPGA hardware emulation.The verification results show that the method can obtain the structural coverage of 90%.

Key words: functional verification, general processor, instruction template, instruction generation, constraint random instruction

摘要： 随着集成电路设计的复杂度越来越高,功能验证成为设计流程中的瓶颈。而通用处理器是集成电路中功能最为复杂的设计之一,对其功能验证提出更高要求。为此,给出一种约束随机指令生成方法,对ARMv8处理器进行模拟验证。从指令集中提取指令模板,用指令模板生成合 法的ARMv8指令,通过调整约束支持各种功能场景的验证。基于结果自动比对的验证环境,对处理器进行充分验证,发现58处设计错误,可用在后续的FPGA硬件仿真中。验证结果表明,该方法可得到90%的结构覆盖率。

关键词: 功能验证, 通用处理器, 指令模板, 指令生成, 约束随机指令

CLC Number: 

• TP031.6