Abstract: With the widespread use of the Internet of Things and embedded devices, the demand for data encryption is growing. Stream cipher algorithms have become an important choice in resource-constrained environments due to their simple implementation and fast encryption/decryption speeds. LILI-128 and LILI-II are typical double-LFSR clock-controlled filter stream cipher algorithms, with similar hardware structures but significant parameter differences. Existing implementations are mostly customized for a single algorithm, resulting in non-reusable resources and a lack of system-level integration. Therefore, this paper proposes a system bus-based reconfigurable LILI cipher algorithm dedicated IP core implementation. This solution uses 128-bit general-purpose shift registers and reuses the same elements to enable reconfiguration for both cipher algorithms. To handle the variable step length of LFSRd, four parallel pre-computation shift register modules are designed, and a data selection unit allows 1-4 step shifts to be completed in a single cycle. It is integrated into the Hummingbird E203 processor’s ICB bus using memory-mapped I/O. Experimental results show that, compared to a pure software implementation on a typical RISC-V Hummingbird E203 platform, this solution reduces the clock cycles needed for cipher execution to just 0.16% of the original method, while boosting throughput over 400 times to 91.42 Mbps. FPGA implementation uses 936 LUTs with an operating frequency of 234.47 MHz, and ASIC implementation in 65 nm technology further increases throughput to 478.4 Mbps with a total area of only 21,297 μm². Although it slightly increases resource usage compared to a single-algorithm hardware implementation, this solution can flexibly switch between LILI-128 and LILI-II within the same architecture and supports efficient interaction with the processor, achieving a good balance between flexibility, processing efficiency, and hardware cost.

摘要： 随着物联网与嵌入式设备的广泛应用，数据加密需求日益增长，序列密码算法因其实现简单、加解密速度快等优势成为资源受限环境下的重要选择。LILI-128与LILI-II是典型的双LFSR钟控滤波序列密码算法，硬件结构相似但参数差异大，现有实现方案多为单一算法定制，资源无法复用且缺乏系统级集成。因此，本文提出一种基于系统总线的可重构LILI密码算法专用IP核实现方案，该方案采用128位通用移位寄存器与复用相同项的方式实现两种密码算法的可重构，针对LFSRd步长可变的特点，设计四个并行预计算移位寄存器模块，通过数据选择单元在单周期内实现1～4步的移位，并以内存映射I/O的方式集成至蜂鸟E203处理器的ICB总线。实验结果表明，在典型的RISC-V处理器蜂鸟E203平台与纯软件实现相比，本方案完成密码算法实现执行时钟周期数缩减至原有方案的0.16%，吞吐率提升超过400倍，达91.42 Mbps；基于FPGA实现时资源占用936个LUTs，工作频率234.47 MHz；在65 nm工艺下ASIC实现吞吐率进一步提升至478.4 Mbps，综合面积仅21 297 μm²。虽较单一算法硬件实现时资源消耗略有增加，但本方案可在同一架构下灵活切换LILI 128与LILI II，并支持与处理器高效交互，在灵活性、处理效率与硬件开销之间实现了良好平衡。