Abstract:
According to the top-down design method, this paper introduces the system architecture of one 8-bit RISC MCU IP core, analyzes the technique for realization of pipeline and jump-instruction. It presents a plan of building a virtual instruction memory module for simulation of MCU IP core, and a method to initial the memory are shown, to advance simulation efficiency of MCU IP core.
Key words:
RISC,
MCU,
Simulation,
Instruction memory module
摘要： 介绍了一种8位RISC MCU IP核的体系结构，采用自顶向下的设计思想对其进行模块划分，分析了流水线及跳转指令操作的实现，提出建立虚拟指令存储器模块对MCU IP核仿真的方案，并给出对虚拟指令存储器初始化的方法，该方法提高了MCU IP软核仿真的效率。
关键词:
RISC,
MCU,
仿真,
指令存储器模块
WANG Zuqiang; ZHANG Hua; LI Ling. New Method of Simulation for 8-bit RISC MCU IP Soft Core[J]. Computer Engineering, 2007, 33(06): 248-249.
王祖强;张 华;李 玲. 8位RISC MCU IP软核仿真的新方法[J]. 计算机工程, 2007, 33(06): 248-249.