Abstract:
In this paper, Verilog HDL---a hardware description language is introduced. The process of designing digital logic system by verilog HDL is presented, compared with the traditional digital logic system design method.
摘要： 介绍硬件描述语言Verilog-HDL。通过与传统的数字逻辑系统的设计方法进行比较，展现了硬件描述语言Verilog-HDL设计数字逻辑电路的优越性。
关键词:
Verilog HDL,
硬件描述语言,
电子设计自动化,
逻辑电路
CLC Number:
MA Chao，LEE Ying，YANG Ming. Design Digital Logic Circuit by Verilog - HDL[J]. , 2000, 26(12): 110-112.
马朝,李颖,杨明. 用Verilog-HDL设计数字逻辑系统[J]. , 2000, 26(12): 110-112.