[1] 刘嘉勇.应用密码学[M].北京:清华大学出版社, 2008. LIU J Y.Applied cryptography[M].Beijing:Tsinghua University Press, 2008.(in Chinese) [2] JIAO L, LIN Y.Stream cipher designs:a review[J].Science China Information Sciences, 2020, 63(3):80-104. [3] 孟涛, 戴紫彬.可重构S盒运算单元的设计与实现[J].电子技术应用, 2007, 33(5):139-139. MENG T, DAI Z B.Design and implementation of reconfigurable S-box computing unit[J].Application of Electronic Technique, 2007, 33(5):139-141.(in Chinese) [4] 常忠祥, 陈卓.可重构S盒替换单元研究与设计[J].微电子学与计算机, 2018, 35(12):125-128, 132. CHANG Z X, CHEN Z.Research and design of reconfigurable S-box replacement unit[J].Microelectronics and Computer, 2018, 35(12):125-128, 132.(in Chinese) [5] 李兆奇.面向分组密码算法的粗粒度可重构架构高能效设计与优化[D].南京:东南大学, 2017. LI Z Q.Energy efficient design and optimization of coarse grained reconfigurable architecture for block cipher algorithm[D].Nanjing:Southeast University, 2017.(in Chinese) [6] 郭怡惠, 李森森, 戴紫彬, 等.RISC微处理器S盒替换指令扩展[J].微电子学与计算机, 2014, 31(5):53-57. GUO Y H, LI S S, DAI Z B, et al.S-box replacement instruction extension of RISC microprocessor[J].Microelectronics and Computer, 2014, 31(5):53-57.(in Chinese) [7] 张肖强.基于复合域运算的AES密码电路优化设计方法研究[D].南京:南京航空航天大学, 2016. ZHANG X Q.Research on optimization design method of AES cipher circuit based on compound field operation[D].Nanjing:Nanjing University of Aeronautics and Astronautics, 2016.(in Chinese) [8] MAXIMOV A, EKDAHL P.New circuit minimization techniques for smaller and faster AES S-Boxes[J].IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019, 32(4):91-125. [9] 张学颖.对称密码有限域运算模块可重构设计技术研究[D].郑州:解放军信息工程大学, 2010. ZHANG X Y.Research on reconfigurable design technology of symmetric cipher finite field operation module[D].Zhengzhou:PLA University of Information Engineering, 2010.(in Chinese) [10] SATPATHY S, SURESH V, MATHEW S, et al.220MV-900MV 794/584/754/GBPS/W reconfigurable GF(24)2 AES/SMS4/camellia symmetric-key cipher accelerator in 14NM tri-gate CMOS[C]//Proceedings of 2018 IEEE Symposium on VLSI Circuits.Washington D.C., USA:IEEE Press, 2018:158-167. [11] 黄荫钊.基于FPGA的低延迟Grain-128a算法设计与实现[D].西安:西安电子科技大学, 2019. HUANG Y Z.Design and implementation of low latency grain-128a algorithm based on FPGA[D].Xi'an:Xi'an University of Electronic Science and Technology, 2019.(in Chinese) [12] 纪祥君, 陈迅, 戴紫彬, 等.一种改进的非线性布尔函数硬件设计与实现[J].计算机应用与软件, 2014, 31(7):283-285, 302. JI X J, CHEN X, DAI Z B, et al.Hardware design and implementation of an improved nonlinear Boolean function[J].Computer Applications and Software, 2014, 31(7):283-285, 302.(in Chinese) [13] 常忠祥, 戴紫彬, 李伟.面向密码算法的非线性布尔函数实现技术研究[J].电子技术应用, 2014, 40(7):61-64. CHANG Z X, DAI Z B, LI W.Research on implementation technology of nonlinear Boolean function for cryptographic algorithm[J].Application of Electronic Technology, 2014, 40(7):61-64.(in Chinese) [14] 戴紫彬, 王周闯, 李伟, 等.可重构非线性布尔函数利用率模型研究与硬件设计[J].电子与信息学报, 2017, 39(5):1226-1232. DAI Z B, WANG Z C, LI W, et al.Reconfigurable nonlinear Boolean function utilization model research and hardware design[J].Acta electronica Sinica, 2017, 39(5):1226-1232.(in Chinese) [15] 张振民.序列密码非线性组件的设计研究[D].西安:西安电子科技大学, 2014. ZHANG Z M.Research on the design of nonlinear component of sequence cipher[D].Xi'an:Xi'an University of Electronic Science and Technology, 2014.(in Chinese) [16] 李声涛.分组密码中S盒的设计与分析[D].长沙:国防科学技术大学, 2004. LI S T.Design and analysis of S-box in block cipher[D].Changsha:University of Defense Science and Technology, 2004.(in Chinese) [17] NOGAMI Y, NEKADO K, TOYOTA T, et al.Mixed bases for efficient inversion in F(22)2 and conversion matrices of sub bytes of AES[C]//Proceedings of International Workshop on Cryptographic Hardware and Embedded Systems.Berlin, Germany:Springer, 2010:156-168. [18] 刘健.两类密码组件的实现优化方法研究[D].郑州:战略支援部队信息工程大学, 2019. LIU J.Research on optimization m_ethod of two kinds of cryptographic components[D].Zhengzhou:PLA Strategic Support Force Information Engineering University, 2019.(in Chinese) [19] 戴强, 戴紫彬, 李伟.基于增强型延时感知CSE算法的AES S盒电路优化设计[J].电子学报, 2019, 47(1):129-136. DAI Q, DAI Z B, LI W.Optimization design of AES S-box circuit based on enhanced delay sensing CSE algorithm[J].Acta Electronica Sinica, 2019, 47(1):129-136.(in Chinese) [20] 刘元锋.RISC架构微处理器扩展对称密码处理指令的研究[D].郑州:解放军信息工程大学, 2006. LIU Y F.Research on RISC architecture microprocessor extending symmetric cipher processing instruction[D].Zhengzhou:PLA Information Engineering University, 2007.(in Chinese) |