摘要： 介绍了一种用FPGA来快速实现硬件IP核的AES算法的方法,采用Xilinx公司的VirtexXCV-1000-6器件,并给出了时序仿真图,结果表明了其有效性。

关键词: AES, IP, 集成的系统芯片

Abstract: This paper introduces a successful FPGA implementation of the hardware IP core of AES, using the Virtex XCV-1000-6 apparatus of Xilinx and provides the simulation result. The result shows its efficiency.

中图分类号: 

• TN402