Design and Implementation of RISC-Ⅴ Extended Ⅰnstruction Set Supporting FPGA Dynamic Reconfiguration

doi:10.19678/j.issn.1000-3428.0069267

Abstract

Abstract:

Currently, dynamic refactoring is implemented by configuring it through on-chip interfaces, usually using the dynamic refactoring control Intellectual Property (IP) core provided by the official Field Programmable Gate Array (FPGA), and connected to the processor through the system bus. This method consumes a significant amount of static logic resources and limits the frequency of the on-chip interfaces. To address these issues, this study proposes the design concept of abstracting an FPGA as large-scale memory. A Dynamic Partial ReConfiguration (DPRC) dynamic reconstruction control instruction set and supporting Application Programming Interface (API) are constructed to optimize the usage of logic resources and eliminate buffer latency. The instruction set is implemented based on the original RV32IMC, using microinstruction sequences to control the on-chip interface part. By tightly coupling with the data path, logic resource usage is reduced, and a parameterized multicycle scheme is used to optimize the timing and ensure generality. Experimental results show that, compared with traditional methods, the dynamic reconstruction function in this system reduces the logical resource usage by 84% and increases the frequency by 312%. Compared with the original processor, the addition of an extended instruction set increases the resource usage of the processor alone by 5%. In the worst case, the impact of the extended part on the clock cycle is less than 0.2 ns, which shows that this dynamic reconstruction control scheme has the characteristics of low cost and high clock frequency.

Key words: RISC-Ⅴ instruction set, extended instruction set, dynamic reconfiguration, FPGA technology, large scale memory

摘要：

目前实现动态重构的常用方法是通过片上接口进行配置, 一般采用现场可编程门阵列(FPGA)官方提供的动态重构控制知识产权(IP)核, 并通过系统总线与处理器相连。这种方法会占用较多静态部分的逻辑资源, 并且限制了片上接口的运行频率。针对这些问题, 提出将FPGA抽象为大规模存储器的设计理念, 构建DPRC动态重构控制指令集及配套应用程序编程接口(API), 以优化逻辑资源占用量, 消除缓冲延迟。指令集的实现以原有RV32IMC为基础, 采用微指令序列控制片上接口部分, 通过与数据通路紧密耦合来减少逻辑资源使用量, 使用参数化多周期方案优化时序并确保通用性。实验结果表明, 与传统方法相比, 该系统中动态重构功能相关逻辑资源占用量减少84%, 频率提高312%。相较于原有处理器, 添加扩展指令集后处理器自身资源占用量仅增加5%, 最差情况下扩展部分对时钟周期的影响小于0.2 ns, 表明该动态重构控制方案具有低成本、高主频的特性。

关键词: RISC-Ⅴ指令集, 扩展指令集, 动态重构, FPGA技术, 大规模存储器

ZHOU Xuanjin, CAI Gang, HUANG Zhihong. Design and Implementation of RISC-Ⅴ Extended Ⅰnstruction Set Supporting FPGA Dynamic Reconfiguration[J]. Computer Engineering, 2025, 51(5): 229-238.

周炫锦, 蔡刚, 黄志洪. 支持FPGA动态重构的RISC-Ⅴ扩展指令集设计与实现[J]. 计算机工程, 2025, 51(5): 229-238.

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Figures/Tables 12

Fig.1 DPRC dynamic reconfiguration system architecture

Fig.2 ICAP interface and logic relationship

Fig.3 Processor architecture that supports DPRC extended instruction set

Fig.4 Microinstruction control flow

Fig.5 FPGA dynamic reconfiguration extended instruction set test system

Fig.6 Minimum clock cycle test results

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