Abstract: This paper presents a kind of systolic array architecture which is used to realize BP algorithm. It designs a characters recognition system in FPGA based on this systolic array architecture. The micro architectures of the computing components in FPGA are analyzed. Experiment results show that realizing BP algorithm in FPGA can improve the study and recognition speed.

Key words: Neural networks, Systolic array architecture, BP algorithm, FPGA

摘要： 提出了一种用于实现BP神经网络的串行输入串行输出的脉动阵列结构，在FPGA上实现了基于该阵列结构的用于进行“A－Z” 的印刷体字符识别系统。文中对FPGA中运算部件的微结构进行了讨论。实验结果表明，与软件实现相比用FPGA实现神经网络算法能够极大地提高BP网络的学习和分类速度。

关键词: 神经网络, 脉动阵列结构, BP算法, FPGA

CLC Number: 

• TP 311