Abstract:
In this paper, a VLSI design and implementation of a high-speed MPEG2 IQ unit is described. It utilizes a high-speed Wallace-booth multiplier to improve the circuit operation speed. At a frequency of 75 MHz, the unit is synthesized by 0.35μm CMOS cell library with Synopsys software. It costs 3500 gates and the delay of critical path is 10.3ns. The IQ can be used in HDTV video decoder.
摘要： 介绍了一种适用于高清晰度电视解码芯片的MPEG2标准逆量化器的VLSI的设计和实现方法。采用了快速的wallace-booth乘法器提高电路的计算速度。在 75 MHz时钟频率下,用Synopsys软件进行仿真,在0.35μm工艺CMOS单元库下进行综合。电路规模为 3500门左右 ,关键路径延时为10.3ns,其性能完全满足高清晰度数字电视解码要求。
关键词:
wallace-booth乘法器,
逆量化,
MPEG2,
高清晰度数字电视
CLC Number:
WU Yuyan, RONG Mengtian, Mao Junfa. VLSI Design and Implementation of a High-speed MPEG2 IQ Unit[J]. , 2004, 30(13): 188-190.
吴钰焱,戎蒙恬,毛军发. 高速MPEG2逆量化器的VLSI的设计和实现[J]. , 2004, 30(13): 188-190.