Abstract:
This paper introduces a successful FPGA implementation of the hardware IP core of AES, using the Virtex XCV-1000-6 apparatus of Xilinx and provides the simulation result. The result shows its efficiency.
摘要： 介绍了一种用FPGA来快速实现硬件IP核的AES算法的方法,采用Xilinx公司的VirtexXCV-1000-6器件,并给出了时序仿真图,结果表明了其有效性。
关键词:
AES,
IP,
集成的系统芯片
CLC Number:
WANG Xin,MA Zitang,XU Jinfu. Hardware IP Core of AES[J]. , 2005, 31(02): 154-156.
王欣,马自堂,徐金甫. 一种AES算法的快速硬件实现[J]. , 2005, 31(02): 154-156.